A.1 A Novel Compliance Testing Technology based on Automatic Detection of Misinterpretations
Allon Adir, Sigal Asaf, Itai Jaeger, Laurent Fournier (IBM)

A.2 Verification of the AMBA Protocol
Samin Ishtiaq (ARM)

A.3 IEEE-754/2007: So Many Choices
Dan Zuras (Group70)

B.1 An Automated Compositional Approach on Sequential Equivalence Checking
In-Ho Moon, Per Bjesse, and Carl Pixley (Synopsys)

B.2 Fast Verification of Complex, but Reasonable, Datapaths
Ted Stanion (Synopsys)

B.3 Transaction Level to RTL Formal Compliance Checking
Carl Pixley (Synopsys)

Session C: High Level Test
Session Chair: TBD

C.1 Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
H.-M. Koo, Prabhat Mishra, Jayanta Bhadra*, Magdy S. Abadir* (University of Florida and *Freescale)

C.2 Software-based on-line test of communication peripherals in processor-based systems for automotive applications
A. Manzone, M. Osella, P. Bernardi, L. Bolzani, M. Violante, M. Sonza Reorda (Centro Ricerche Fiat and Politecnico di Torino)

C.3 Circuit Profiling Mechanisms for High-level ATPG
Jorge Campos and Hussain Al-Asaad (University of California at Davis)

E.1 Test Implications of in-package/on-chip VRM
T. M. Mak (Intel)

E.2 Statistical Static Timing Analysis Considering The Impact of Power Supply Noise In VLSI Circuits
Hyun Sung Kim and D. M. H. Walker (Texas A&M)

E.3 Fault-tolerant Design in the Era of Variability, Degradation, and Soft Errors
Ming Zhang, T M Mak, Kee Sup Kim (Intel)

Dinner & Social Event (TBD)

Introduction Modern Debug Issues and Problems (10 mins)
Al Crouch (Inovys)

F.1 On-ATE Diagnosis
Jason Doege (DA Tech)

F.2 Embedded Compression Diagnosis
Nikhil Dakwala (Stridge)

F.3 Real Fault Insertion for Evaluating Diagnosis Tools
John Potter (Inovys)

F.4 Debug Support for Scalable System-on-Chip
Jianmin Zhang, Ming Yan, Sikun Li (National University of Defense Technology, China)

Session G: High Level Modeling, Verification and Debug
Session Chair: Jim Holt (Freescale)

G.1 uADL: A Microarchitecture Description and Modeling Tool
Hangsheng Wang, Brian Kahne (Freescale)

G.2 RFSM: A Rendezvous of TLM and RTL
Wei Qin (Boston University)

G.3 Workload Slicing For Characterizing New Features in High Performance Microprocessors
Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese (Freescale)

G.4 Deep vs. Shallow, Kernel vs. Language - What is Better for Heterogeneous Modeling in SystemC?
Hiren D. Patel and Sandeep K. Shukla (Virginia Tech)

Panel: Strategies for Convergence Between Design Validation, Test and Debug
Organizers: Vivekananda Vedula (Intel), Jay Bhadra (Freescale)
Moderator: Magdy Abadir (Freescale)

Participants:
Jacob A. Abraham (University of Texas at Austin)
Michael Hsiao (Virginia Tech)
Gary Miller (Freescale)
Praveen Parvathala (Intel)
Carl Pixley (Synopsys)
Others: TBD.

Session H: Error Diagnosis
Session Chair: Alper Sen (Freescale)

H.1 Abstraction and Refinement Techniques in Automated Design Debugging
Sean Safarpour, Andreas Veneris (University of Toronto)

H.2 On Reducing the Global State Graph for Verification of Distributed Computations
Arindam Chakraborty and Vijay Garg (University of Texas at Austin)

H.3 Diagnosing Silicon Failures Based on Functional Test Patterns
C-C. Yen, T. Lin, H. Lin, K. Yang*, T. Liu*, Y.-C. Hsu* (Springsoft Inc. and *Novas Software Inc.)

Session I: Functional Test and validation
Session Chair: Mark Nodine (Intrinsity)

I.1 Functional Test Selection for High Volume Manufacturing
Vijay Gangaram, Deepa Bhan, James K Caldwell (Intel)

I.2 A Probabilistic Analysis For Fault Detectability of Code Coverage Metrics
Sreekumar V. Kodakara, Deepak A. Mathaikutty*, Ajit Dingankar**, Sandeep Shukla*, and David Lilja (University of Minnesota, *Virginia Tech and **Intel)

I.3 Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation
Tamarah Arons, Elad Elster, Terence Murphy, Eli Singerman (Intel)

I.4 Test Calculation for Logic and Delay Faults in Digital Circuits
József Sziray (Széchenyi University, Hungary)